In this post I will give an explanation about my research project which became my master dissertation. It is a complicated subject which uses technical terms.
My dissertation’s title is “Optimized System Design of Radiofrequency Receivers Based on Consumption Power Models”, that is, a circuit design block method of a radiofrequency receiver to the receiver consume the minimum energy possible without harm the performance. For a long time the block design was based on the designer’s experience and this design not always is the most economical in power consumption. This work is about only the receiver’s analog part.
Receiver
First I have to choose a receiver architecture to define the circuit blocks to be designed, the chosen architecture is the Zero-IF, because it has the less number of blocks, therefore consume less power. Here is the RF transceiver in Zero-IF, the receiver above and the transmitter below.
Chosen the architecture, were selected the circuit blocks to be designed, the blocks are: RF filter, LNA (Low Noise Amplifier), Mixer, Base Band Filter, VGA (Voltage Gain Control) and ADC (Analog Digital Converter).
The adopted standard is the LTE, a forth generation standard, in the parameters distribution I had to respect the gain, noise figure and IIP3 limits.
Method
To prove the method effectiveness I choose two models very different for each other, I make arbitrary distributions to see the power consumption and later I applied the optimization. The optimization method is an algorithm whose fluxogram is below, it make random distributions of gain, signal-noise rate and signal-noise + distortion rate, calculate the power consumption and repeat the cycle a number of times. After apply the optimization, calculate the power consumption and repeat a number of times. To more information see in the document I put in the end of post to download.
Simulation
There is a table with the models, the distributions and how much the algorithm reduces the power consumption.
| Model 1 | Model 2 | |
| Uniform (Case 1) | 15,37mW | 447,6mW |
| 1-x to SNR_{deg} and SNDR_{deg} (Case 2) | 6,72mW | 341,29mW |
| 1-x to SNR_{deg} and x to SNDR_{deg} (Case 3) | 11,64mW | 325,86mW |
| Average | 11,24mW | 371,58mW |
| With optimization | 1,90mW | 190,35mW |
| Reduction comparing to average | 83% | 48,8% |
The power consumption graphics of each circuit block to comparison, the model 1 is (a) and the model 2 is (b).
To know more with more details about my thesis, here is the complete thesis in pdf, only available in Portuguese.
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